Electronic devices are ubiquitous in society and can be found in everything from wristwatches to computers. The complexity and sophistication of these electronic devices usually increases with each generation. For example, newer generations of microprocessors often implement multiple processing “cores” on a single integrated circuit (IC), where each core may be capable of concurrently executing at least some of the program code. While implementing these multiple cores on a single IC may be advantageous in that the processor may be capable of increased processing power, implementing these multiple cores on a single IC may present new challenges in terms of designing and building the IC. One aspect of IC design that may be especially problematic for multi-core processors is chip routing.
The term “chip routing”, as used herein, refers to the final stages of IC design where the various constituent blocks of the IC are brought together in a chip floor plan and are coupled together. Chip routing often involves taking constituent blocks in an IC design (e.g., processor core blocks, memory controller blocks, network controller block, etc.), placing the constituent blocks within the confines of a minimum physical area (i.e., creating a proposed floor plan), and routing electrical connections between the different blocks and between the pins of the IC. Once the constituent blocks have been placed and routed, the timing of signals between various blocks in the proposed floor plan needs to be “verified” using computer simulations. In other words, if the IC is expected to operate at a desired frequency, computer simulations may be performed to verify that the proposed floor plan and routing do not prevent IC operation at the desired frequency. If the computer simulations show that the proposed routing in the proposed floor plan prevents the IC from operating at the desired frequency, electrical signals must be re-routed to improve the timing of the signals. Other reasons that the routing process may need to be started over again include: if the number or orientation of a constituent blocks changes while the proposed floor plan is being created, if the manufacturing process in the foundry changes while the floor plan is being created, and/or if the desired operating frequency of the IC changes. Needless to say, because there may be many connections between blocks in conventional ICs (e.g., a multi-bit bus between cores in a multi-core processor), the desire to pack the constituent blocks of the IC into the smallest possible area, and aggressive timing goals (e.g., desire to run the multi-core processor as fast as possible), each iteration of the chip re-routing process may consume a considerable amount of time